// `include "top_define.v"
module table_ram_addr_convert(
                              input clk,
                              input rst_n,
                              output reg CPU_read_table_q_vld ,
                              input [11:0] CPU_read_table_addr,
                              input CPU_read_table_rd_en,
                              output reg[31:0] CPU_read_table_q,
                              input CPU_write_table_wr_en,
                              input [31:0] CPU_write_table_data,
                              
                              output [9:0] table_ram_addr_convert,
                              output reg [71:0] table_ram_data_convert,
                              output reg table_ram_wr_en_convert,
                              // output table_ram_wr_en_convert,
                              input  [71:0] table_ram_q_toconvert  

                             );
//地址表中的数据{ 2'd0, sur_mac(48), sour_port(8), time_val, time_now(13) }
reg CPU_write_table_wr_en_dl1;
reg CPU_read_table_rd_en_d1,CPU_read_table_rd_en_d2;
reg [11:0] CPU_read_table_addr_dl1,CPU_read_table_addr_dl2;
assign table_ram_addr_convert  = (!CPU_write_table_wr_en_dl1) ? CPU_read_table_addr[9:0] : CPU_read_table_addr_dl1[9:0]; // 2022.5.17, xym
// assign table_ram_addr_convert  = (!CPU_write_table_wr_en_dl1) ? CPU_read_table_addr[11:2] : CPU_read_table_addr_dl1[11:2];
// assign table_ram_wr_en_convert = CPU_write_table_wr_en_dl1;
always @ (  posedge clk or negedge rst_n )
  begin
    if(~rst_n)
      table_ram_data_convert <= 72'd0;
    else 
      case ( CPU_read_table_addr_dl1[11:10] ) // 2022.5.17, xym
      // case ( CPU_read_table_addr_dl1[1:0] )
        2'b11:
          begin
            table_ram_data_convert <= { 6'd0, 16'd0, 32'd0, CPU_write_table_data[17:0] };// 18b, 2022.5.17, xym
            // table_ram_data_convert <= { table_ram_q_toconvert[71:18], CPU_write_table_data[17:0] };
            table_ram_wr_en_convert <= 1'b0 ;
          end
        2'b00:
          begin
            table_ram_data_convert <= { 6'd0, 16'd0, CPU_write_table_data, table_ram_data_convert[17:0]};// 32b, 2022.5.17, xym
            // table_ram_data_convert <= { table_ram_q_toconvert[71:50], CPU_write_table_data, table_ram_q_toconvert[17:0]};
            table_ram_wr_en_convert <= 1'b0 ;
          end
        2'b01:
          begin
            table_ram_data_convert <= { 6'd0, CPU_write_table_data[15:0], table_ram_data_convert[49:0]};// 16b, 2022.5.17, xym
            // table_ram_data_convert <= { table_ram_q_toconvert[71:66], CPU_write_table_data[15:0], table_ram_q_toconvert[49:0]};
            table_ram_wr_en_convert <= CPU_write_table_wr_en ;
          end
	    default:
          begin
            table_ram_data_convert <= table_ram_data_convert;
            table_ram_wr_en_convert <= 1'b0 ;
          end
      endcase
  end

always @ ( posedge clk or negedge rst_n )
  begin
    if(~rst_n)begin
      CPU_read_table_q <= 32'b0;
      CPU_read_table_q_vld <= 1'b0;
    end else if(CPU_read_table_rd_en_d2)begin
      case ( CPU_read_table_addr_dl2[11:10] )
      // case ( CPU_read_table_addr_dl2[1:0] )
        2'b11:begin
          CPU_read_table_q <= { 13'd0, table_ram_q_toconvert[17:0] };
          CPU_read_table_q_vld <= 1'b1;
        end
        2'b00:begin
          CPU_read_table_q <= { table_ram_q_toconvert[49:18] };
          CPU_read_table_q_vld <= 1'b1;
        end
        2'b01:begin
          CPU_read_table_q <= { 16'd0, table_ram_q_toconvert[65:50] };
          CPU_read_table_q_vld <= 1'b1;
        end
        default:begin
          CPU_read_table_q <= CPU_read_table_q;
          CPU_read_table_q_vld <= 1'b0;
        end
      endcase
    end else begin
      CPU_read_table_q <= CPU_read_table_q;
      CPU_read_table_q_vld <= 1'b0;
    end 
  end

always @ ( posedge clk or negedge rst_n )
if (~rst_n)
  CPU_read_table_addr_dl1 <=  1'b0;
else
  CPU_read_table_addr_dl1 <=  CPU_read_table_addr;
always @ ( posedge clk or negedge rst_n )
if (~rst_n)
  CPU_read_table_addr_dl2 <=  1'b0;
else
  CPU_read_table_addr_dl2 <=  CPU_read_table_addr_dl1;
always @ ( posedge clk or negedge rst_n )
if (~rst_n)
  CPU_read_table_rd_en_d1 <=  1'b0;
else
  CPU_read_table_rd_en_d1 <=  CPU_read_table_rd_en;
always @ ( posedge clk or negedge rst_n )
if (~rst_n)
  CPU_read_table_rd_en_d2 <=  1'b0;
else
  CPU_read_table_rd_en_d2 <=  CPU_read_table_rd_en_d1;
always @ ( posedge clk or negedge rst_n )
if (~rst_n)
  CPU_write_table_wr_en_dl1 <=  1'b0;
else
  CPU_write_table_wr_en_dl1 <=  CPU_write_table_wr_en;

endmodule
